StarCore Unveils StarCore V5 Architecture: Scalable to Over 1 GHz, Offers Balance of Features to Power Next-Generation Multimedia Handset and High-Performance Infrastructure Applications
SAN JOSE, Calif.—(BUSINESS WIRE)—Oct. 24, 2005—
StarCore today announced the StarCore(TM) V5
architecture, its latest processor core architecture that is capable
of driving the highest performance wireless handsets and portable
multimedia devices.
Key Features of the StarCore V5 Architecture
In addition to all of the unique features of the previous StarCore
processor architectures, the StarCore V5 architecture introduces many
innovations, including 47 new instructions, which improve support for
compilers and operating systems, enhance single-instruction
multiple-data (SIMD) processing, and deliver highest-in-class
multimedia and Viterbi performance. The new V5 instruction set, built
on StarCore's proprietary variable length instruction set (VLES)
technology, provides a unique combination of DSP performance and code
density competitive with the most efficient microcontrollers. Thanks
to a fully-interlocked pipeline and to branch-prediction logic, the
StarCore V5 architecture is designed to maximize performance of
compiled code and optimize high-frequency implementations with less
costly memories. Enhanced multimedia and communication instructions
provide further optimization for communication and consumer
applications, and a memory-management system makes it easy to support
sophisticated operating systems, such as Linux(R). The new V5
architecture is binary-code compatible with all previous StarCore
architectures, providing protection for customers' investment in
software development.
Performance
StarCore optimized both the architecture and the implementation,
to be scalable to 1GHz operating frequency in a typical 90nm
high-performance process. Devices based on the StarCore V5
architecture are ideally suited to the latest multimedia applications,
such as high-quality, real-time video encoding and decoding. At the
same time, the architecture allows customers concerned with longer
battery life to implement their V5-compliant devices in an extremely
low-power process and still have a performance margin never achieved
before with a processor offering this level of DSP capability.
"We are very pleased to see the V5 architecture on StarCore's
roadmap, as it aligns well with our product roadmaps," said Sumit
Sadana, senior vice president, Strategy and Business Development for
Freescale. "StarCore's strategy of increasing performance while
driving down power consumption and maintaining binary-code
compatibility makes this a logical choice for some of our next
generation platforms. The V5 architecture will enable us to deliver
power-optimized products, while improving time to market by leveraging
the software investment in the architecture platform."
"StarCore's V5 architecture, with its higher performance and
video-media oriented instruction set, is right on target for the
emerging multimedia gateway market that Agere is focused on," said
Craig Garen, Director of Engineering for Agere System's Telecom
Division. "The enhanced instruction set, combined with higher clock
rates is ideal for optimizing the number of available voice and video
channels in the smallest board space for applications, such as remote
access platforms, media servers, and multimedia gateways."
"When we started developing this architecture, we faced a dilemma:
our infrastructure customers demanded the highest performance and
channel density in a cost-effective package, whereas our mobile
handset customers expected maximum battery life and acceleration of
multimedia and communications functions; everyone wanted a competitive
architecture that's easy to program, is binary-compatible with their
existing software base, and is straightforward to integrate in their
SoCs," said Alex Bedarida, General Manager of StarCore. "Our technical
team was able to deliver all this, and even more. The instruction set
of the StarCore V5 architecture makes software-centric implementations
of complex applications possible, eliminating the need for separate
Viterbi and multimedia accelerators. In addition, removal of the
programming restrictions that traditionally afflict DSPs makes using
the V5 architecture as easy as programming a general-purpose
microcontroller."
Availability
StarCore processor cores and system-level IP blocks are licensed
in a synthesizable format and can be targeted to any silicon foundry
technology. Processor cores and subsystems based on the StarCore V5
architecture will be available in early 2006.
About StarCore
StarCore is a leader in the development of high-performance
processor architectures, cores, and subsystems for the communications
and consumer electronics industries. For more information on StarCore
and its intellectual property and services, visit the company's
website at http://www.starcore-dsp.com.
Contact:
StarCore, Austin
Allen Hyman, 512-682-8558
email: Email Contact
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